EC3023 VLSI DESIGN SYLLABUS | ANNA UNIVERSITY BE MEDICAL ELECTRONICS ENGINEERING 8TH SEMESTER SYLLABUS REGULATION 2008 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY 8TH SEMESTER B.E MEDICAL ELECTRONICS ENGINEERING DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,PREVIOUS YEAR QUESTION PAPERS,MODEL QUESTION PAPERS, CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI, TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009
EC3023 VLSI DESIGN L T P C
3 0 0 3
UNIT I MOS TECHNOLOGY 9
Chip Design Hierarchy- IC Layers –Photolithography and Pattern Transfers- Basic
MOS Transistors-CMOS Fabrication – Submicron CMOS Process –Masks and Layout
–CMOS Design Rules: Lambda based layout- Types of rules- SCMOS Design Rule
set II.
UNIT II MOSFET TRANSISTOR 9
MOSFET operation - MOSFET switch model and square law model – MOSFET
parasitic-– MOSFET SPICE Modeling-CMOS Inverter: Voltage Transfer curve- Layout-
Body Effect-Latch up problem in CMOS circuits-Latch up prevention-
UNIT III CMOS LOGIC GATES DESIGN AND LAYOUT 9
NAND and NOR Gates – Complex Logic Gates –Tri state circuits – Large FETs-
Transmission Gate and Pass Transistor Logic-Standard Cell design: Cell hierarchy-Cell
libraries.
UNIT IV STORAGE ELEMENTS AND DYNAMIC LOGIC CIRCUITS 9
SR Latch- Bit Level Register –D Type Flip Flop –Dynamic D Flip Flop –The Static RAM
Cell –Dynamic Logic – Domino Logic – SR Logic –Dynamic Memories
79
UNIT V VHDL 9
VHDL Program Structure- concurrent code – sequential code - Variables- signals and
Constants-VHDL Operators -VHDL Description of Combinational Networks: Adders –
Modeling Flip Flop using VHDL Processes – VHDL Model for Multiplexer –Modeling a
sequential Machine-
TOTAL: 45 PERIODS
REFERENCES
1. John P Uyemura- “ Chip Design for Submicron VLSI:CMOS layout and simulation”
Thomson India Edition- 2006(unit I to IV)
2. Charles H Roth-”Digital System Design Using VHDL”- Thomson business
Information India Pvt Ltd-2006 (Unit V)
3. Kamran Eshraghian- Douglas A Pucknell Sholeh Eshraghian “Essentials of VLSI
Circuits and Systems”- Prentice Hall of India Pvt Ltd- 2006
4. Volnei A Pedroni-”Circuit design with VHDL”- Prentice Hall of India Pvt Ltd- 2005
5 Wayne Wolf,” Modern VLSI Design – System On Chip”, PHI 2006, 3e, New Delhi
EC3023 VLSI DESIGN L T P C
3 0 0 3
UNIT I MOS TECHNOLOGY 9
Chip Design Hierarchy- IC Layers –Photolithography and Pattern Transfers- Basic
MOS Transistors-CMOS Fabrication – Submicron CMOS Process –Masks and Layout
–CMOS Design Rules: Lambda based layout- Types of rules- SCMOS Design Rule
set II.
UNIT II MOSFET TRANSISTOR 9
MOSFET operation - MOSFET switch model and square law model – MOSFET
parasitic-– MOSFET SPICE Modeling-CMOS Inverter: Voltage Transfer curve- Layout-
Body Effect-Latch up problem in CMOS circuits-Latch up prevention-
UNIT III CMOS LOGIC GATES DESIGN AND LAYOUT 9
NAND and NOR Gates – Complex Logic Gates –Tri state circuits – Large FETs-
Transmission Gate and Pass Transistor Logic-Standard Cell design: Cell hierarchy-Cell
libraries.
UNIT IV STORAGE ELEMENTS AND DYNAMIC LOGIC CIRCUITS 9
SR Latch- Bit Level Register –D Type Flip Flop –Dynamic D Flip Flop –The Static RAM
Cell –Dynamic Logic – Domino Logic – SR Logic –Dynamic Memories
79
UNIT V VHDL 9
VHDL Program Structure- concurrent code – sequential code - Variables- signals and
Constants-VHDL Operators -VHDL Description of Combinational Networks: Adders –
Modeling Flip Flop using VHDL Processes – VHDL Model for Multiplexer –Modeling a
sequential Machine-
TOTAL: 45 PERIODS
REFERENCES
1. John P Uyemura- “ Chip Design for Submicron VLSI:CMOS layout and simulation”
Thomson India Edition- 2006(unit I to IV)
2. Charles H Roth-”Digital System Design Using VHDL”- Thomson business
Information India Pvt Ltd-2006 (Unit V)
3. Kamran Eshraghian- Douglas A Pucknell Sholeh Eshraghian “Essentials of VLSI
Circuits and Systems”- Prentice Hall of India Pvt Ltd- 2006
4. Volnei A Pedroni-”Circuit design with VHDL”- Prentice Hall of India Pvt Ltd- 2005
5 Wayne Wolf,” Modern VLSI Design – System On Chip”, PHI 2006, 3e, New Delhi
No comments:
Post a Comment
Any doubt ??? Just throw it Here...