VL9212 VLSI DESIGN TECHNIQUES SYLLABUS | ANNA UNIVERSITY ME APPLIED ELECTRONICS 1ST SEM SYLLABUS REGULATION 2009 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY FIRST SEMESTER M.E APPLIED ELECTRONICS DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,PREVIOUS YEAR QUESTION PAPERS,MODEL QUESTION PAPERS, CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI, TIRUNELVELI,COIMBATORE), 2009 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009
VL9212 VLSI DESIGN TECHNIQUES L T P C
3 0 0 3
UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY 9
NMOS and PMOS transistors, Threshold voltage- Body effect- Design equations-
Second order effects. MOS models and small signal AC characteristics. Basic CMOS
technology.
UNIT II INVERTERS AND LOGIC GATES 9
NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient
characteristics , switching times, Super buffers, Driving large capacitance loads, CMOS
logic structures , Transmission gates, Static CMOS design, dynamic CMOS design.
UNIT III CIRCUIT CHARACTERIZATION AND PERFORMANCE
ESTIMATION 9
Resistance estimation, Capacitance estimation, Inductance, switching characteristics,
transistor sizing, power dissipation and design margining. Charge sharing .Scaling.
5
UNIT IV VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL
PHYSICAL DESIGN 9
Multiplexers, Decoders, comparators, priority encoders, Shift registers. Arithmetic
circuits – Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers.
Physical design – Delay modelling ,cross talk, floor planning, power distribution. Clock
distribution. Basics of CMOS testing.
UNIT V VERILOG HARDWARE DESCRIPTION LANGUAGE 9
Overview of digital design with Verilog HDL, hierarchical modeling concepts, modules
and port definitions, gate level modeling, data flow modeling, behavioral modeling, task
& functions, Test Bench.
TOTAL : 45 PERIODS
REFERENCES:
1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson
Education ASIA, 2nd edition, 2000.
2. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons,
Inc., 2002.
3. Samir Palnitkar, “Verilog HDL”, Pearson Education, 2nd Edition, 2004.
4. Eugene D.Fabricius, “Introduction to VLSI Design”, McGraw Hill International
Editions, 1990.
5. J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2nd Edition, 2001.
6. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.
7. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.
VL9212 VLSI DESIGN TECHNIQUES L T P C
3 0 0 3
UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY 9
NMOS and PMOS transistors, Threshold voltage- Body effect- Design equations-
Second order effects. MOS models and small signal AC characteristics. Basic CMOS
technology.
UNIT II INVERTERS AND LOGIC GATES 9
NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient
characteristics , switching times, Super buffers, Driving large capacitance loads, CMOS
logic structures , Transmission gates, Static CMOS design, dynamic CMOS design.
UNIT III CIRCUIT CHARACTERIZATION AND PERFORMANCE
ESTIMATION 9
Resistance estimation, Capacitance estimation, Inductance, switching characteristics,
transistor sizing, power dissipation and design margining. Charge sharing .Scaling.
5
UNIT IV VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL
PHYSICAL DESIGN 9
Multiplexers, Decoders, comparators, priority encoders, Shift registers. Arithmetic
circuits – Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers.
Physical design – Delay modelling ,cross talk, floor planning, power distribution. Clock
distribution. Basics of CMOS testing.
UNIT V VERILOG HARDWARE DESCRIPTION LANGUAGE 9
Overview of digital design with Verilog HDL, hierarchical modeling concepts, modules
and port definitions, gate level modeling, data flow modeling, behavioral modeling, task
& functions, Test Bench.
TOTAL : 45 PERIODS
REFERENCES:
1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson
Education ASIA, 2nd edition, 2000.
2. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons,
Inc., 2002.
3. Samir Palnitkar, “Verilog HDL”, Pearson Education, 2nd Edition, 2004.
4. Eugene D.Fabricius, “Introduction to VLSI Design”, McGraw Hill International
Editions, 1990.
5. J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2nd Edition, 2001.
6. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.
7. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.
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