VL 9211 DSP INTEGRATED CIRCUITS SYLLABUS | ANNA UNIVERSITY ME VLSI DESIGN 1ST SEM SYLLABUS REGULATION 2009 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY FIRST SEMESTER M.E VLSI DESIGN DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,PREVIOUS YEAR QUESTION PAPERS,MODEL QUESTION PAPERS, CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI, TIRUNELVELI,COIMBATORE), 2009 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009
VL 9211 DSP INTEGRATED CIRCUITS LT P C
3 0 0 3
UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES 9
Standard digital signal processors, Application specific IC’s for DSP, DSP systems, DSP
system design, Integrated circuit design. MOS transistors, MOS logic, VLSI process
technologies, Trends in CMOS technologies
UNIT II DIGITAL SIGNAL PROCESSING 9
Digital signal processing, Sampling of analog signals, Selection of sample frequency,
Signal- processing systems, Frequency response, Transfer functions, Signal flow
graphs, Filter structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform,
FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms.
3
UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 9
FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping
of analog transfer functions, Mapping of analog filter structures, Multirate systems,
Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate
filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Roundoff
noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.
UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP
ARCHITECTURES 9
DSP system architectures, Standard DSP architecture, Ideal DSP architectures,
Multiprocessors and multicomputers, Systolic and Wave front arrays, Shared memory
architectures. Mapping of DSP algorithms onto hardware, Implementation based on
complex PEs, Shared memory architecture with Bit – serial PEs.
UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 9
Conventional number system, Redundant Number system, Residue Number System,
Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size,
Complex multipliers, Improved shift-accumulator. Layout of VLSI circuits, FFT processor,
DCT processor and Interpolator as case studies. Cordic algorithm.
TOTAL: 45 PERIODS
REFERENCES
1. Lars Wanhammer, “DSP Integrated Circuits”, 1999 Academic press, New York
2. A.V.Oppenheim et.al, “Discrete-time Signal Processing”, Pearson Education, 2000.
3. Emmanuel C. Ifeachor, Barrie W. Jervis, “ Digital signal processing – A practical
approach”, Second Edition, Pearson Education, Asia.
4. Keshab K.Parhi, “VLSI Digital Signal Processing Systems design and
Implementation”, John Wiley & Sons, 1999.
VL 9211 DSP INTEGRATED CIRCUITS LT P C
3 0 0 3
UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES 9
Standard digital signal processors, Application specific IC’s for DSP, DSP systems, DSP
system design, Integrated circuit design. MOS transistors, MOS logic, VLSI process
technologies, Trends in CMOS technologies
UNIT II DIGITAL SIGNAL PROCESSING 9
Digital signal processing, Sampling of analog signals, Selection of sample frequency,
Signal- processing systems, Frequency response, Transfer functions, Signal flow
graphs, Filter structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform,
FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms.
3
UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 9
FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping
of analog transfer functions, Mapping of analog filter structures, Multirate systems,
Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate
filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Roundoff
noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.
UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP
ARCHITECTURES 9
DSP system architectures, Standard DSP architecture, Ideal DSP architectures,
Multiprocessors and multicomputers, Systolic and Wave front arrays, Shared memory
architectures. Mapping of DSP algorithms onto hardware, Implementation based on
complex PEs, Shared memory architecture with Bit – serial PEs.
UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 9
Conventional number system, Redundant Number system, Residue Number System,
Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size,
Complex multipliers, Improved shift-accumulator. Layout of VLSI circuits, FFT processor,
DCT processor and Interpolator as case studies. Cordic algorithm.
TOTAL: 45 PERIODS
REFERENCES
1. Lars Wanhammer, “DSP Integrated Circuits”, 1999 Academic press, New York
2. A.V.Oppenheim et.al, “Discrete-time Signal Processing”, Pearson Education, 2000.
3. Emmanuel C. Ifeachor, Barrie W. Jervis, “ Digital signal processing – A practical
approach”, Second Edition, Pearson Education, Asia.
4. Keshab K.Parhi, “VLSI Digital Signal Processing Systems design and
Implementation”, John Wiley & Sons, 1999.
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