ET 9011 ADVANCED DIGITAL SYSTEM DESIGN SYLLABUS | ANNA UNIVERSITY ME HIGH VOLTAGE ENGINEERING 1ST SEM SYLLABUS REGULATION 2009 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY FIRST SEMESTER M.E HIGH VOLTAGE ENGINEERING DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,PREVIOUS YEAR QUESTION PAPERS,MODEL QUESTION PAPERS, CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2009 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009
ET 9011 ADVANCED DIGITAL SYSTEM DESIGN L T P C
3 0 0 3
AIM
To expose the students to the fundamentals of digital logic based system design.
OBJECTIVES
To impart knowledge on
i. Basics on Synchronous & Async digital switching design.
ii. Design & realisation of error free functional blocks for digital systems
1. SEQUENTIAL CIRCUIT DESIGN 9
Analysis of Clocked Synchronous Sequential Networks (CSSN) Modelling of CSSN –
State Stable Assignment and Reduction – Design of CSSN – Design of Iterative Circuits
– ASM Chart – ASM Realization, Design of Arithmetic circuits for Fast adder- Array
Multiplier.
2. ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9
Analysis of Asynchronous Sequential Circuit (ASC) – Flow Table Reduction – Races in
ASC – State Assignment Problem and the Transition Table – Design of ASC – Static
and Dynamic Hazards – Essential Hazards – Data Synchronizers – Designing Vending
Machine Controller – Mixed Operating Mode Asynchronous Circuits.
3. FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS 9
Fault Table Method – Path Sensitization Method – Boolean Difference Method – Kohavi
Algorithm – Tolerance Techniques – The Compact Algorithm – Practical PLA’s – Fault in
PLA – Test Generation – Masking Cycle – DFT Schemes – Built-in Self Test.
4. SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES 9
Programming Techniques -Re-Programmable Devices Architecture- Function blocks, I/O
blocks, Interconnects, Realize combinational, Arithmetic, Sequential Circuit with
Programmable Array Logic; Architecture and application of Field Programmable Logic
Sequence.
5. NEW GENERATION PROGRAMMABLE LOGIC DEVICES 9
Foldback Architecture with GAL, EPLD, EPLA , PEEL, PML; PROM – Realization State
machine using PLD – FPGA – Xilinx FPGA – Xilinx 2000 - Xilinx 3000
TOTAL : 45 PERIODS
REFERENCES:
1. Donald G. Givone, “Digital principles and Design”, Tata McGraw Hill 2002.
2. Stephen Brown and Zvonk Vranesic, “Fundamentals of Digital Logic with VHDL
Deisgn”, Tata McGraw Hill, 2002
3. Mark Zwolinski, “Digital System Design with VHDL”, Pearson Education, 2004
4. Parag K Lala, “Digital System design using PLD”, BS Publications, 2003
5. John M Yarbrough, “Digital Logic applications and Design”, Thomson Learning,
2001
6. Nripendra N Biswas, “Logic Design Theory”, Prentice Hall of India, 2001
7. Charles H. Roth Jr., “Fundamentals of Logic design”, Thomson Learning, 2004.
ET 9011 ADVANCED DIGITAL SYSTEM DESIGN L T P C
3 0 0 3
AIM
To expose the students to the fundamentals of digital logic based system design.
OBJECTIVES
To impart knowledge on
i. Basics on Synchronous & Async digital switching design.
ii. Design & realisation of error free functional blocks for digital systems
1. SEQUENTIAL CIRCUIT DESIGN 9
Analysis of Clocked Synchronous Sequential Networks (CSSN) Modelling of CSSN –
State Stable Assignment and Reduction – Design of CSSN – Design of Iterative Circuits
– ASM Chart – ASM Realization, Design of Arithmetic circuits for Fast adder- Array
Multiplier.
2. ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9
Analysis of Asynchronous Sequential Circuit (ASC) – Flow Table Reduction – Races in
ASC – State Assignment Problem and the Transition Table – Design of ASC – Static
and Dynamic Hazards – Essential Hazards – Data Synchronizers – Designing Vending
Machine Controller – Mixed Operating Mode Asynchronous Circuits.
3. FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS 9
Fault Table Method – Path Sensitization Method – Boolean Difference Method – Kohavi
Algorithm – Tolerance Techniques – The Compact Algorithm – Practical PLA’s – Fault in
PLA – Test Generation – Masking Cycle – DFT Schemes – Built-in Self Test.
4. SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES 9
Programming Techniques -Re-Programmable Devices Architecture- Function blocks, I/O
blocks, Interconnects, Realize combinational, Arithmetic, Sequential Circuit with
Programmable Array Logic; Architecture and application of Field Programmable Logic
Sequence.
5. NEW GENERATION PROGRAMMABLE LOGIC DEVICES 9
Foldback Architecture with GAL, EPLD, EPLA , PEEL, PML; PROM – Realization State
machine using PLD – FPGA – Xilinx FPGA – Xilinx 2000 - Xilinx 3000
TOTAL : 45 PERIODS
REFERENCES:
1. Donald G. Givone, “Digital principles and Design”, Tata McGraw Hill 2002.
2. Stephen Brown and Zvonk Vranesic, “Fundamentals of Digital Logic with VHDL
Deisgn”, Tata McGraw Hill, 2002
3. Mark Zwolinski, “Digital System Design with VHDL”, Pearson Education, 2004
4. Parag K Lala, “Digital System design using PLD”, BS Publications, 2003
5. John M Yarbrough, “Digital Logic applications and Design”, Thomson Learning,
2001
6. Nripendra N Biswas, “Logic Design Theory”, Prentice Hall of India, 2001
7. Charles H. Roth Jr., “Fundamentals of Logic design”, Thomson Learning, 2004.
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