EC9314 VLSI DESIGN TECHNIQUES SYLLABUS | ANNA UNIVERSITY ME ECE 1ST SEM SYLLABUS REGULATION 2009 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY FIRST SEMESTER M.E ECE ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,PREVIOUS YEAR QUESTION PAPERS,MODEL QUESTION PAPERS, CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI, TIRUNELVELI,COIMBATORE), 2009 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009
EC9314 VLSI DESIGN TECHNIQUES L T P C
3 0 0 3
UNIT - I VLSI DESIGN PROCESS & MOS TRANSISTOR THEORY AND PROCESS
TECHNOLOGY (9)
VLSI Design Process – Architectural Design – Logical Design – Physical Design – Layout Styles
–Full custom, Semicustom approaches. NMOS and PMOS transistors, Threshold voltage- Body
effect- Design equations- Second order effects. MOS models and small signal AC
characteristics. Basic CMOS technology.
6
UNIT - II INVERTERS AND LOGIC GATES (9)
NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient characteristics ,
switching times, Super buffers, Driving large capacitance loads, CMOS logic structures ,
Transmission gates, Static CMOS design, dynamic CMOS design.
UNIT - III CIRCUIT CHARACTERISATION & PERFORMANCE ESTIMATION (9)
Resistance estimation, Capacitance estimation, Inductance, switching characteristics, transistor
sizing, power dissipation and design margining. Charge sharing .Scaling.
UNIT - IV VLSI SYSTEM COMPONENTS CIRCUITS (9)
Multiplexers, Decoders, comparators, priority encoders, Shift registers. Arithmetic circuits –
Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers
UNIT - V VERILOG HARDWARE DESCRIPTION LANGUAGE (9)
Overview of digital design with Verilog HDL, hierarchical modelling concepts, modules and port
definitions, gate level modelling, data flow modelling, behavioral modelling, task & functions,
Test Bench.
TOTAL: 45 PERIODS
REFERENCES:
1. Jan M Rabaey, “ Digital Integrated Circuits” Prentice Hall of India, 2002.
2. Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits- Analysis and
Design”,Tata McGraw Hill,2003.
3. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson
Education ASIA, 2nd edition, 2000.
4. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc.,
2002.
5. Samir Palnitkar, “Verilog HDL”, Pearson Education, 2nd Edition, 2004
6. Eugene D.Fabricius, Introduction to VLSI Design McGraw Hill International Editions, 1990
7. J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2nd Edition, 2001
8. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.
9. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.
EC9314 VLSI DESIGN TECHNIQUES L T P C
3 0 0 3
UNIT - I VLSI DESIGN PROCESS & MOS TRANSISTOR THEORY AND PROCESS
TECHNOLOGY (9)
VLSI Design Process – Architectural Design – Logical Design – Physical Design – Layout Styles
–Full custom, Semicustom approaches. NMOS and PMOS transistors, Threshold voltage- Body
effect- Design equations- Second order effects. MOS models and small signal AC
characteristics. Basic CMOS technology.
6
UNIT - II INVERTERS AND LOGIC GATES (9)
NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient characteristics ,
switching times, Super buffers, Driving large capacitance loads, CMOS logic structures ,
Transmission gates, Static CMOS design, dynamic CMOS design.
UNIT - III CIRCUIT CHARACTERISATION & PERFORMANCE ESTIMATION (9)
Resistance estimation, Capacitance estimation, Inductance, switching characteristics, transistor
sizing, power dissipation and design margining. Charge sharing .Scaling.
UNIT - IV VLSI SYSTEM COMPONENTS CIRCUITS (9)
Multiplexers, Decoders, comparators, priority encoders, Shift registers. Arithmetic circuits –
Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers
UNIT - V VERILOG HARDWARE DESCRIPTION LANGUAGE (9)
Overview of digital design with Verilog HDL, hierarchical modelling concepts, modules and port
definitions, gate level modelling, data flow modelling, behavioral modelling, task & functions,
Test Bench.
TOTAL: 45 PERIODS
REFERENCES:
1. Jan M Rabaey, “ Digital Integrated Circuits” Prentice Hall of India, 2002.
2. Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits- Analysis and
Design”,Tata McGraw Hill,2003.
3. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson
Education ASIA, 2nd edition, 2000.
4. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc.,
2002.
5. Samir Palnitkar, “Verilog HDL”, Pearson Education, 2nd Edition, 2004
6. Eugene D.Fabricius, Introduction to VLSI Design McGraw Hill International Editions, 1990
7. J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2nd Edition, 2001
8. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.
9. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.
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