EC2357 VLSI DESIGN LAB SYLLABUS | ANNA UNIVERSITY BE ECE ENGINEERING 6TH SEM SYLLABUS REGULATION 2008 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY SIXTH SEMESTER BE
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009
EC2357 VLSI DESIGN LABORATORY L T P C
0 0 3 2
1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers,
address decoders, multiplexers), Test bench creation, functional verification, and
concepts of concurrent and sequential execution to be highlighted.
2. Design Entry and simulation of sequential logic circuits (counters, PRBS generators,
accumulators). Test bench creation, functional verification, and concepts of concurrent
and sequential execution to be highlighted.
3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt.
No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate
count, I/O configuration and pin assignment to be taught in this experiment.
4. Generation of configuration/fuse files for all the blocks/codes developed as part of
Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested for the
blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the
inputs and outputs for each of the blocks must be demonstrated atleast on oscilloscopes
(logic analyzer preferred).
5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of
gain, bandwidth, output impedance and CMRR.
6. Layout of a simple CMOS inverter, parasitic extraction and simulation.
7. Design of a 10 bit number controlled oscillator using standard cell approach, simulation
followed by study of synthesis reports.
8. Automatic layout generation followed by post layout extraction and simulation of the
circuit studied in Expt. No.7
Note 1. For Expt. 1 To 4 can be carried out using Altera (Quartus) / Xilinx (Alliance) /
ACTEL (Libero) tools.
Note 2. For expt. 5-8 introduce the student to basics of IC design. These have to be carried
out using atleast 0.5u CMOS technology libraries. The S/W tools needed Cadence /
MAGMA / Tanner.
EC2357 VLSI DESIGN LABORATORY L T P C
0 0 3 2
1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers,
address decoders, multiplexers), Test bench creation, functional verification, and
concepts of concurrent and sequential execution to be highlighted.
2. Design Entry and simulation of sequential logic circuits (counters, PRBS generators,
accumulators). Test bench creation, functional verification, and concepts of concurrent
and sequential execution to be highlighted.
3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt.
No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate
count, I/O configuration and pin assignment to be taught in this experiment.
4. Generation of configuration/fuse files for all the blocks/codes developed as part of
Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested for the
blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the
inputs and outputs for each of the blocks must be demonstrated atleast on oscilloscopes
(logic analyzer preferred).
5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of
gain, bandwidth, output impedance and CMRR.
6. Layout of a simple CMOS inverter, parasitic extraction and simulation.
7. Design of a 10 bit number controlled oscillator using standard cell approach, simulation
followed by study of synthesis reports.
8. Automatic layout generation followed by post layout extraction and simulation of the
circuit studied in Expt. No.7
Note 1. For Expt. 1 To 4 can be carried out using Altera (Quartus) / Xilinx (Alliance) /
ACTEL (Libero) tools.
Note 2. For expt. 5-8 introduce the student to basics of IC design. These have to be carried
out using atleast 0.5u CMOS technology libraries. The S/W tools needed Cadence /
MAGMA / Tanner.
No comments:
Post a Comment
Any doubt ??? Just throw it Here...