EC2303 COMPUTER ARCHITECTURE AND ORGANIZATION SYLLABUS | ANNA UNIVERSITY ECE 5TH SEMESTER SYLLABUS REGULATION 2008 2011-2012

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EC2303 COMPUTER ARCHITECTURE AND ORGANIZATION SYLLABUS | ANNA UNIVERSITY ECE 5TH SEMESTER SYLLABUS REGULATION 2008 2011-2012 BELOW IS THE ANNA UNIVERSITY FIFTH SEMESTER BE ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT SYLLABUS IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011-2012 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009

EC2303 COMPUTER ARCHITECTURE AND ORGANIZATION L T P C
3 0 0 3
AIM
To discuss the basic structure of a digital computer and to study in detail the
organization of the Control unit, the Arithmetic and Logical unit, the Memory unit and the
I/O unit.
OBJECTIVES
 To have a thorough understanding of the basic structure and operation of a digital
computer.
 To discuss in detail the operation of the arithmetic unit including the algorithms &
implementation of fixed-point and floating-point addition, subtraction, multiplication &
division.
 To study in detail the different types of control and the concept of pipelining.
 To study the hierarchical memory system including cache memories and virtual
memory.
 To study the different ways of communicating with I/O devices and standard I/O
interfaces.
UNIT I INTRODUCTION 9
Computing and Computers, Evolution of Computers, VLSI Era, System Design- Register
Level, Processor Level, CPU Organization, Data Representation, Fixed – Point
Numbers, Floating Point Numbers, Instruction Formats, Instruction Types. Addressing
modes.
UNIT II DATA PATH DESIGN 9
Fixed Point Arithmetic, Addition, Subtraction, Multiplication and Division, Combinational
and Sequential ALUs, Carry look ahead adder, Robertson algorithm, booth’s algorithm,
non-restoring division algorithm, Floating Point Arithmetic, Coprocessor, Pipeline
Processing, Pipeline Design, Modified booth’s Algorithm
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UNIT III CONTROL DESIGN 9
Hardwired Control, Microprogrammed Control, Multiplier Control Unit, CPU Control Unit,
Pipeline Control, Instruction Pipelines, Pipeline Performance, Superscalar Processing,
Nano Programming.
UNIT IV MEMORY ORGANIZATION 9
Random Access Memories, Serial - Access Memories, RAM Interfaces, Magnetic
Surface Recording, Optical Memories, multilevel memories, Cache & Virtual Memory,
Memory Allocation, Associative Memory.
UNIT V SYSTEM ORGANIZATION 9
Communication methods, Buses, Bus Control, Bus Interfacing, Bus arbitration, IO and
system control, IO interface circuits, Handshaking, DMA and interrupts, vectored
interrupts, PCI interrupts, pipeline interrupts, IOP organization, operation systems,
multiprocessors, fault tolerance, RISC and CISC processors, Superscalar and vector
processor.
TOTAL= 45 PERIODS
TEXTBOOKS
1. John P.Hayes, ‘Computer architecture and Organisation’, Tata McGraw-Hill, Third
edition, 1998.
2. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “Computer
Organisation“, V edition, McGraw-Hill Inc, 1996.
REFERENCES
1. Morris Mano, “Computer System Architecture”, Prentice-Hall of India, 2000.
2. Paraami, “Computer Architecture”, BEH R002, Oxford Press.
3. P.Pal Chaudhuri, , “Computer organization and design”, 2nd Ed., Prentice Hall of
India, 2007.
4. G.Kane & J.Heinrich, ‘ MIPS RISC Architecture ‘, Englewood cliffs, New Jersey,
Prentice Hall, 1992.